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isolated, 4 a dual-channel gate driver data sheet adum3220 / ADUM3221 rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2010C2012 analog devices, inc. all rights reserved. technical support www.analog.com features 4 a peak output current precise timing characteristics 60 ns maximum isolator and driver propagation delay 5 ns maximum channel-to-channel matching high junction temperature operation: 125c 3.3 v to 5 v input logic 4.5 v to 18 v output drive uvlo at 2.5 v v dd1 adum3220a / ADUM3221a uvlo at 4.1 v v dd2 adum3220b / ADUM3221b uvlo at 7.0 v v dd2 thermal shutdown protection at >150c output shoot-through logic protection on the adum3220 default low output high frequency operation: dc to 1 mhz cmos input logic levels high common-mode transient immunity: >25 kv/s enhanced system-level esd performance per iec 61000-4-x safety and regulatory approvals ul recognition 2500 v rms for 1 minute per ul 1577 csa component acceptance notice #5a vde certificate of conformity din v vde v 0884-10 (vde v 0884-10):2006-12 v iorm = 560 v peak small footprint and low profile narrow body, rohs-compliant, 8-lead soic 5 mm 6 mm 1.6 mm qualified for automotive applications applications isolated synchronous dc-to-dc converters mosfet/igbt gate drivers general description the adum3220 / ADUM3221 1 are isolated, 4 a dual-channel gate drivers based on the analog devices, inc., i coupler? technology. combining high speed cmos and monolithic transformer technol- ogy, these isolation components provide outstanding performance characteristics superior to the alternatives, such as the combination of pulse transformers and gate drivers. the adum3220 / ADUM3221 provide digital isolation in two independent isolation channels. they have a maximum propagation delay of 60 ns and 5 ns channel-to-channel matching. in comparison to gate drivers that employ high voltage level translation method- ologies, the adum3220 / ADUM3221 offer the benefit of true, galvanic isolation between the input and each output, enabling voltage translation across the isolation barrier. the adum3220 has shoot-through protection logic, which prevents both outputs from being on at the same time, whereas the ADUM3221 allows both outputs to be on at the same time. both parts offer a default output low characteristic as required for gate drive applications. the adum3220 / ADUM3221 operate with an input supply voltage ranging from 3.0 v to 5.5 v, providing compatibility with lower voltage systems. the outputs of the adum3220a / ADUM3221a can be operated at supply voltages from 4.5 v to 18 v. the outputs of the adum3220b / ADUM3221b can be operated at supply voltages from 7.6 v to 18 v. the junction temperature of the adum3220/ ADUM3221 is specified from ?40c to +125c. functional block diagrams encode encode decode and level shift decode and level shift v dd1 v ia v ib gnd 1 v dd2 v oa v ob gnd 2 1 2 3 4 8 7 6 5 adum3220 08994-001 encode encode decode and level shift decode and level shift v dd1 v ia v ib gnd 1 v dd2 v oa v ob gnd 2 1 2 3 4 8 7 6 5 ADUM3221 08994-102 figure 1. figure 2. 1 protected by u.s. patents 5,952,849; 6,873,065; 7,075,239.
adum3220/ADUM3221 data sheet rev. c | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 function al block diagrams ............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electric al characteristics 5 v operation ................................ 3 electrical characteristics 3.3 v operation ............................ 4 package characteristics ............................................................... 5 regulatory information ............................................................... 5 insulation and safety - related specifications ............................ 5 din v vde v 08 84- 10 (vde v 0884 - 10) insulation characteristics .............................................................................. 6 recommended operating conditions ...................................... 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ..............................8 typical performance characteristics ..............................................9 applications information .............................................................. 12 pc board layout ........................................................................ 12 propagation delay - related parameters ................................... 12 thermal limitations and switch load characteristics ......... 12 output load characteristics ..................................................... 12 dc correctness and magnetic field immunity .......................... 13 power consumption .................................................................. 14 insulation lifetime ..................................................................... 14 outline dimensions ....................................................................... 15 ordering guide .......................................................................... 15 automotive products ................................................................. 15 revision history 10 /12 rev. b to rev. c changes to fe atures section and general description section .... 1 created hyperlink for safety and regulatory approvals entry in features section ................................................................. 1 added outpu t pulsed source resistance parameter and output pulsed sink resistance parameter to table 1 .......... 3 added output pulsed source resistance parameter and output pulsed sink resistance parameter to table 2 .......... 4 added ic junction - to - ambient thermal resistance parame ter to table 3 ......................................................................... 5 changes to introductory sentence of regulatory information section ......................................................................... 5 change d supply voltage ranges parameter in table 8 ............... 7 changes to table 9 ............................................................................ 7 changes to table 11 and table 12 .................................................. 8 added figure 17 and figure 18 ; renumbered sequentially ..... 11 mo ved figure 21 ............................................................................. 12 changes to power consumption section and insulation lifetime section .............................................................................. 14 changes to ordering guide .......................................................... 15 added automotive products section ........................................... 15 3/11 rev. a to rev. b added adum3220brz and ADUM3221brz models .... universal changes to features secti on and general description section .. 1 changes to table 1 ............................................................................. 3 changes to table 2 ............................................................................. 4 added figure 17 and figure 18; renumbered sequentially ..... 11 changes to ordering guide .......................................................... 14 1 /1 1 rev. 0 to rev. a added ADUM3221 ............................................................. universal changes to features section and general de scription section .. 1 added figure 2; renumbered sequentially ................................... 1 change s to endnote 3, endnote 4, and endnote 5, table 1 ......... 3 changes to endnote 3, endnote 4, and endnote 5, table 2 ......... 4 changes to table 8 ............................................................................. 7 change s to figure 4 , table 10, and table 11 .................................. 8 added table 12; renumbered sequentially ................................... 8 added figure 8 ................................................................................... 9 change to figure 19 and dc correctness and magnetic field immunity section ........................................................................... 12 changes to ordering guide .......................................................... 14 4 /10 revision 0: initial version
data sheet adum3220/ADUM3221 rev. c | page 3 of 16 specifications electrical character istics 5 v operation all volt a ges are relative to their respective ground. 4.5 v v dd1 5.5 v , 4.5 v v dd2 18 v , unless stated otherwise . all minimum/ maximum specifications apply over t j = ? 40 c to + 125 c . all typical specifications are at t j = 25 c, v dd1 = 5 v, v dd2 = 1 0 v. swit ching specifications are tested with cmos signal levels. table 1 . parameter symbol min typ max unit test conditions /comments dc specifications i nput supply current , two channels, quiescent i ddi (q) 1. 2 1.5 ma ou tput supp ly current , two channels , quiescent i ddo (q) 4.7 10 ma total supply current, two channels 1 dc to 1 m hz v dd1 supply current i dd1 (q) 1.4 1.7 ma dc to 1 mhz logic signal freq uency v dd2 supply current i dd2 (q) 11 17 ma dc to 1 mhz logic signa l freq uency input currents i ia , i ib ?10 +0.01 +10 a 0 v v ia , v ib v dd1 logic high input threshold v ih 0.7 v dd1 v logic low input threshold v il 0.3 v dd1 v logic high output voltages v oah , v o b h v dd 2 ? 0.1 v dd2 v i ox = ?20 m a, v ix = v ixh l ogic low output voltages v oal , v obl 0.0 0.1 5 v i ox = + 20 m a, v ix = v ixl undervoltage lockout, v dd2 supply adum3220a / ADUM3221a positive - going thres hold v dd2uv+ 4. 1 4 . 4 v negative - going threshold v dd2uv ? 3.2 3 . 7 v hysteresis v dd2uvh 0.4 v adum3220b / ADUM3221b positive - going threshold v dd2uv+ 7.0 7.5 v negative - going threshold v dd2uv? 6.0 6.5 v h ysteresis v dd2uvh 0.5 v output short - circuit pulsed current 2 i oa(sc) , i ob(sc) 2.0 4.0 a v dd2 = 10 v output pulsed source resistance r oa , r ob 0.3 1.3 3.0 ? v dd2 = 10 v output pulsed sink resistance r oa , r ob 0.3 0.9 3.0 ? v dd2 = 10 v switching specif ications pulse width 3 pw 50 ns c l = 2 nf, v dd2 = 10 v data rate 4 1 m hz c l = 2 nf, v dd2 = 10 v propagation delay 5 t dlh , t dhl 35 45 6 0 ns c l = 2 nf, v dd2 = 10 v ; s ee figure 20 t dlh , t dhl 36 50 68 ns c l = 2 nf, v dd2 = 4.5 v ; see figure 20 propagation delay skew 6 t psk 12 ns c l = 2 nf, v dd2 = 10 v ; see figure 20 channel - to - channel matching 7 t pskcd 1 5 ns c l = 2 nf, v d d2 = 10 v ; see figure 20 t pskcd 1 7 ns c l = 2 nf, v dd2 = 4.5 v ; see figure 20 output rise /fall time (10% to 90%) t r / t f 14 20 2 5 n s c l = 2 nf, v dd2 = 10 v ; see figure 20 t r / t f 14 22 28 ns c l = 2 nf, v dd2 = 4.5 v; see figure 20 dynamic input supply current per channel i ddi(d) 0.05 ma/mbps v dd2 = 10 v dynamic output supply current per channel i ddo(d) 1.5 ma/mbps v dd2 = 10 v refresh rate f r 1.2 mbps 1 the supply current values for both channels are combined when running at identical data rates. output supply c urrent values are specified with no output load present. the supply current associated with an individual channel operating at a given data rate can be calculated as described in the power consumption section. see figure 9 and figure 10 for total v dd1 and v dd2 supply currents as a function of frequency . 2 short - circuit duration less than 1 s. average power must conform to the limit shown in the absolute maximum ratings section. 3 the minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed. 4 the maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed. 5 t dlh propagation delay is measured from the time of the input rising logic high threshold, v ih , to the output rising 10% threshold of the v ox signal. t dhl propagation delay is measured from the input falling logic low threshold, v il , to the output falling 90% threshold of the v ox signal. see figure 20 for waveforms of propagation delay parameters. 6 t psk is the magnitude of the worst - case difference in t dlh and/or t dhl that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. see figure 20 for waveforms of propagation delay parameters. 7 channe l - to - channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the sa me side of the isolation barrie r.
adum3220/ADUM3221 data sheet rev. c | page 4 of 16 electrical character istics 3 .3 v o peration all voltages are relative to their respective ground. 3.0 v v dd1 3.6 v, 4.5 v v dd2 18 v , unless stated otherwise. all minimum/ max imum specifications apply over t j = ? 40 c to + 125 c . all typical specifications are at t j = 25c, v dd1 = 3.3 v, v dd2 = 10 v. switching specifications are tested with cmos signal levels. table 2 . p arameter symbol min typ max unit te st conditions /comments dc specifications input supply current, two channel s , quiescent i ddi (q) 0.7 1.0 ma output supply current, two channel s , quiescent i ddo (q) 4. 7 10 ma total supply current, two channels 1 dc to 1 m hz v dd1 supp ly current i dd1 (q) 0.8 1. 0 ma dc to 1 mhz logic signal frequency v dd2 supply current i dd2 (q) 11 1 7 ma dc to 1 mhz logic signal frequency input currents i ia , i ib ?10 +0.01 +10 a 0 v v ia , v ib v dd1 logic high input threshold v ih 0.7 v dd1 v logic low input threshold v il 0.3 v dd1 v logic high output voltages v oah , v o b h v dd2 ? 0.1 v dd2 v i ox = ?20 ma, v ix = v ixh logic low output voltages v oal , v obl 0.0 0.15 v i ox = + 20 ma, v ix = v ixl undervoltage lockout, v dd2 supply adum3220a / ADUM3221a positive - going threshold v dd2uv+ 4.1 4.4 v negative - go ing threshold v dd2uv? 3.2 3.7 v hysteresis v dd2uvh 0.4 v adum3220b / ADUM3221b positive - going threshold v dd2uv+ 7.0 7.5 v negative - going threshold v dd2uv? 6.0 6.5 v hysteresis v dd2uvh 0.5 v output short - circuit pulsed current 2 i oa(sc) , i ob(sc) 2.0 4.0 a v dd2 = 10 v output pulsed source resistance r oa , r ob 0.3 1.3 3.0 ? v dd2 = 10 v output pulsed sink resistance r oa , r ob 0.3 0.9 3.0 ? v dd2 = 10 v switching s pecifications pulse width 3 pw 50 ns c l = 2 nf, v dd2 = 10 v data rate 4 1 m hz c l = 2 nf, v dd2 = 10 v propagation delay 5 t dlh , t dhl 3 6 4 8 6 2 ns c l = 2 nf, v dd2 = 10 v ; s ee figure 20 t dlh , t dhl 37 53 72 ns c l = 2 nf, v dd2 = 4.5 v ; see figure 20 propagation delay skew 6 t psk 12 ns c l = 2 nf, v dd2 = 10 v ; see figure 20 channel - to - channel matching 7 t pskcd 1 5 ns c l = 2 n f, v dd2 = 10 v ; see figure 20 t pskcd 1 7 ns c l = 2 nf, v dd2 = 4.5 v ; see figure 20 out put rise/fall time (10% to 90%) t r /t f 14 20 25 ns c l = 2 nf, v dd2 = 10 v ; see figure 20 t r /t f 14 22 28 ns c l = 2 nf, v dd2 = 4.5 v ; see figure 20 dynamic i nput supply current per channel i ddi(d) 0.0 2 5 ma/mbps v dd2 = 10 v dynamic output supply curren t per channel i ddo(d) 1.5 ma/mbps v dd2 = 10 v refresh rate f r 1.1 mbps 1 the supply current values for both channels are combined when running at identical data ra tes. output supply current values are specified with no output load present. the supply current associated with an individual channel operating at a given data rate can be calculated as described in the power consumption section . see figure 9 and figure 10 for total v dd1 and v dd2 supply currents as a function of frequency . 2 short - circuit duration less than 1 s. average power must c onform to the limit shown in the absolute maximum ratings section. 3 the minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed . 4 the maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed . 5 t dlh propagation delay is measured from the time of the input rising logic high threshold, v ih , to the output rising 10% threshold of the v ox signal. t dhl propagation delay is measured fro m the input falling logic low threshold, v il , to the output falling 90% threshold of the v ox signal. see figure 20 for waveforms of propagation delay parameters. 6 t psk is the magnitude of the worst - case difference in t dlh and/or t dhl that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. see figure 20 for waveforms of propagation delay parameters. 7 channel - to - channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the sa me side of the isolation barrier.
data sheet adum3220/ADUM3221 rev. c | page 5 of 16 package characterist ics table 3 . parameter symbol min typ max unit test conditions /comments resistance (input - to - output) 1 r i - o 10 12 ? capacitance (input -to - output) 1 c i - o 1.0 pf f = 1 mhz input capacitance c i 4.0 pf ic junction - to - case thermal resistance, side 1 jci 46 c/w thermocouple located at center of package underside ic junction - to - cas e thermal resistance, side 2 jco 41 c/w thermocouple located at center of package underside ic junction - to - ambient thermal resistance ja 85 c/w thermocouple located at center of package underside 1 the device is considered a 2 - te rminal device; pin 1 through pin 4 are shorted together, and pin 5 through pin 8 are shorted together. regulatory informati on the adum3220 / ADUM3221 a re a pprov ed by the organizations listed in table 4 . table 4 . ul csa vde recognized u nder ul 15 77 component recognition program 1 approved under csa component acceptance notice #5a certified according to din v vde v 0884 - 10 (vde v 0884 - 10): 2006 - 12 2 single/ basic 2500 v rms isolation voltage basic insulation per csa 60950 - 1 - 03 and iec 60950 - 1, 40 0 v rms (566 v peak) maximum working voltage functional insulation per csa 60950 - 1 - 03 and iec 60950- 1, 800 v rms (1131 v peak) maximum working voltage reinforced insulation, 560 v peak file e214100 file 205078 file 2471900 - 4880 - 0001 1 in accordance with ul 1577, each adum3220 / ADUM3221 is p roof tested by applying an insulation test voltage 3000 v rms for 1 second (current leakage detection limit = 5 a). 2 in accordance with din v vde v 0884 - 10 , each adum3220/ ADUM3221 is proof tested by applying an insulation test voltage 1050 v peak for 1 second (partial discharge detection limit = 5 pc). an asterisk (*) marking branded on the component designates din v vde v 0884 - 10 approval. insulation and saf ety - related specificatio ns table 5 . parameter symbol value unit test conditions/comments rate d dielectric insulation voltage 2500 v rms 1 minute duration minim um external air gap (clearance) l(i01) 4.90 min mm measured from inpu t terminals to output terminals, shortest distance through air minim um external tracking (creepage) l(i02) 4.01 min mm measured from input terminals to output terminals, shortest distance path along body minimum in ternal gap (internal clearance) 0.017 m in mm insulation distance through insulation tracking resistan ce (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1)
adum3220/ADUM3221 data sheet rev. c | page 6 of 16 din v vde v 0884 - 10 (vde v 0884 - 10) i nsulati on characteristics these isolators are suitable for reinforced isolation only within the safety limit data. maintenance of the safety data is en sured by protective circuits. the asterisk ( * ) marking on the package denote s din v vde v 0884 - 10 approval for a 560 v peak working voltage. table 6 . description test conditions /comments symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 560 v peak input - to - output test voltage, method b1 v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc v pr 1050 v peak input - t o - output test voltage, method a v iorm 1.6 = v pr , t m = 6 0 sec, partial discharge < 5 pc v pr after envi ronmental tests subgroup 1 896 v peak after input and/or safety test s subgroup 2 and subgroup 3 v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5 pc v pr 672 v peak highest allowable overvoltage transient overvoltage, t tr = 10 sec v tr 4000 v peak s afety - limiting values maximum value allowed in the event of a failure (see figure 3 ) case temperature t s 150 c side 1 current i s1 160 ma side 2 current i s2 47 ma insulation resistance at t s v io = 500 v r s >10 9 ? case temperature (c) safety-limiting current (ma) 0 0 200 180 100 80 60 40 20 50 100 150 200 side 2 side 1 120 140 160 08994-002 figure 3. thermal derating curve; dependence of safety - limiting values on case temperature, pe r din v vde v 0884 - 10 (safety - limiting current is defined as the average current at maximum v dd ) recommended operatin g condit ions table 7 . parameter symbol min max unit operating junction temperature t j ?40 +125 c supply voltages 1 v dd1 3.0 5.5 v v dd2 4.5 18 v v dd1 rise time t vdd1 1 v/s common - mode transient immunity, input to output ? 2 5 + 2 5 k v/ s input signal rise and fall times 1 ms 1 all voltages a re relative to their respective ground. see the dc correctness and magnetic field immunity section for information about immunity to external magnetic fields.
data sheet adum3220/ADUM3221 rev. c | page 7 of 16 absolute maximum rat ings ambient temperature = 25c, unless otherwise noted. table 8 . parameter rating storage temperature ( t st ) ?55c to +150c operating temperature ( t j ) ?40c to +150c supply voltage ranges 1 v dd1 ?0.5 v to +7.0 v v dd 2 ?0.5 v to +2 0 v input voltage range ( v ia , v ib ) 1, 2 ?0.5 v to v ddi + 0.5 v output voltage range ( v oa , v ob ) 1, 2 ?0.5 v to v ddo + 0.5 v average output current per pin ( i o ) 3 ?23 ma to +23 ma comm on - mode transients, ( cm h , cm l ) 4 ?100 kv/s to +100 kv/s 1 all voltages are relative to their respective ground. 2 v ddi and v ddo refer to the supply voltages on the input and output sides of a given channel, respectively. 3 see figure 3 for information about maximum allowable current for various temperatures. 4 refers to common - mode transients across the insulation barrier. common - mode transients exceeding the absolute maximum rating can cause latch - up or perman ent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sec tion of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 9 . maximum continuous working voltage 1 parameter max unit constraint ac bipolar vo ltage 2 565 v peak 50- year minimum lifetime ac unipolar voltage 3 1131 v peak 50- year minimum lifetime dc voltage 4 1131 v peak 50- year minimum lifetime 1 refers to the continuous voltage magnitude imposed across the isolation barrier. see the insulation lifetime section for more information . 2 see figure 24. 3 see figure 25. 4 see figure 26. esd caution
adum3220/ADUM3221 data sheet rev. c | page 8 of 16 pin configuration and function descrip tions v dd1 1 v ia 2 v ib 3 gnd 1 4 v dd2 8 v oa 7 v ob 6 gnd 2 5 adum3220/ ADUM3221 top view (not to scale) 08994-003 figure 4. pin configuration table 10. pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1, 3.0 v to 5.5 v. 2 v ia logic input a. 3 v ib logic input b. 4 gnd 1 ground 1. ground reference for isolator side 1. 5 gnd 2 ground 2. ground reference for isolator side 2. 6 v ob logic output b. 7 v oa logic output a. 8 v dd2 supply voltage for isolator s ide 2, 4.5 v to 18 v. table 11. truth table , adum3220 (positive logic) 1 v ia input v ib input v dd1 s tate v dd2 s tate v oa output v ob output notes l l powered powered l l l h powered p owered l h h l powered powered h l h h powered powered l l x x unpowered powered l l outputs return to the input state within 1 s of v dd1 p ower restoration . x x powered unpowered l l outputs return to the input state within 1 s of v dd 2 power resto ration . 1 x = dont care, l = low, h = high. table 12 . truth table , ADUM3221 (positive logic) 1 v ia input v ib input v dd1 state v dd2 state v oa output v ob output notes l l powered powe red l l l h powered powered l h h l powered powered h l h h powered powered h h x x unpowered powered l l outputs return to the input state within 1 s of v dd1 p ower restoration . x x powered unpowered l l outputs return to the input state within 1 s of v dd 2 power restoration. 1 x = dont care, l = low, h = high.
data sheet adum3220/ADUM3221 rev. c | page 9 of 16 typical performance characteristics ch1 5v ch2 2v m40ns 2.5gsps 10k points ch2 7.2v t 22.2% ? ? 08994-004 1 2 ch2 = v o (2v/div) ch1 = v i (5v/div) figure 5. output waveform for 2 nf l oad with 10 v output supply ch1 5v ch2 2v m40ns 2.5gsps 10k points ch2 7.2v t 21.4% ? ? 1 2 ch2 = v o (2v/div) ch1 = v i (5v/div) 08994-005 figure 6. output waveform for 1 nf l oad with 10 v output supply ch1 5v ch2 2v m40ns 2.5gsps 10k points ch2 7.2v t 22.1% ? ? 1 2 ch2 = v o (2v/div) ch1 = v i (5v/div) 08994-006 figure 7. output waveform for 1 nf l oad with 5 ? series resistance and 10 v output supply 300 0 50 100 150 200 250 0 200 400 600 800 1000 gate charge (nc) switching frequency (khz) v dd2 = 15v v dd2 = 10v v dd2 = 8v v dd2 = 5v 08994-107 figure 8 . typical maximum load vs. switching frequency (r gate = 1 ? ) 0 0.5 1.0 1.5 2.0 0 0.25 0.50 0.75 1.00 frequenc y (mhz) v dd1 = 5v v dd1 = 3.3v i dd1 current (ma) 08994-015 figure 9 . typical i dd1 supply current vs. frequency 0 10 20 30 40 50 60 70 80 0 0.25 0.50 0.75 1.00 frequenc y (mhz) v dd2 = 5v v dd2 = 10v i dd2 current (ma) v dd2 = 15v 08994-016 figure 10 . typical i dd2 supply current vs. frequency with 2 nf load
adum3220/ADUM3221 data sheet rev. c | page 10 of 16 08994-017 0 10 20 30 40 50 60 ?40 ?20 0 20 40 60 80 100 120 140 pro p ag a tion del a y (ns) junction temper a ture (c) figure 11 . typical propagation delay vs. tempera ture 0 10 20 30 40 50 60 3.0 3.5 4.0 4.5 5.0 5.5 propagation delay (ns) input supp l y vo lt age (v) t dlh t dhl 08994-018 figure 12 . typical propagation delay v s. input supply voltage, v dd2 = 10 v 0 10 20 30 40 50 60 5 7 9 1 1 13 15 17 pro p ag a tion del a y (ns) output supp l y vo lt age (v) t dlh t dhl 08994-019 figure 13 . typical propagation delay vs. output supply voltage, v dd1 = 5 v 08994-020 0 5 10 15 20 25 30 5 7 9 1 1 13 15 17 rise/ f al l time (ns) output supp l y vo lt age (v) rise time fall time figure 14 . typ ical rise/fall time variation vs. output supply voltage 08994-021 0 1 2 3 4 5 5 7 9 11 13 15 17 propagation delay channel-to-channel matching (ns) output supply voltage (v) pd match t dhl pd match t dlh figure 15 . typical propagation delay channel - to- channel matching vs. output supply voltage 08994-022 0 1 2 3 4 5 ?40 ?20 0 20 40 60 80 100 120 140 pro p ag a tion del a y channel- t o-channe l ma tching (ns) junction temper a ture (c) pd match t dlh pd match t dhl figure 16 . typical propagation delay channel - to- ch annel matching vs. temperature, v dd2 = 10 v
data sheet adum3220/ADUM3221 rev. c | page 11 of 16 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 4 6 8 10 12 14 16 18 r out (?) output supp l y vo lt age (v) v out so u r c e r e s is t an c e v out sin k r e s is t an c e 08994- 1 16 figure 17 . typical output source resistance vs. output supply voltage 0 1 2 3 4 5 6 7 8 4 6 8 10 12 14 16 18 output supp l y vo lt age (v) so u r c e i out sin k i out 08994- 1 17 m a xi m u m s o u r c e /s i n k cu r r e n t ( a ) figure 18 . typical maximum source/sink current vs. output supply voltage
adum3220/ADUM3221 data sheet rev. c | page 12 of 16 applica tion s information pc board layout the adum3220 / ADUM3221 digital isolator s require no exter - nal interface circuitry for the logic interfaces. power supply bypas sing is required at the input and output supply pins , as shown in figure 19. use a small ceramic capacitor with a value from 0.01 f to 0.1 f to provide a good high frequency bypass . on the output power supply pin , v dd2 , it is recommended that a 10 f capacitor also be added to provide the charge required to drive the gate capacitance at the adum3220 / ADUM3221 outputs. on the output supply pin , the use of vias with the bypass capacitor should be avoided , or multiple via s should be used to reduce the inductance in the bypassing. the total lead length between both ends of the smaller capacitor and the input or output power s upply pin should not exceed 20 mm. v dd1 v ia v ib v oa v ob gnd 1 v dd2 gnd 2 08994-023 figure 19 . recommended pcb layou t propagation delay - related parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. the prop agation delay to a logic low output can differ from the propagatio n delay to a logic high output. t he adum3220 / ADUM3221 specify t d lh as the time between the inp ut rising high logic threshold, v ih , and the output rising 10% threshold (see figure 20 ) . like wise , the falling propagation delay , t dhl , is defined as the time between the input falling logic low threshold , v il , an d the output falling 90% threshold. the rise and fall times are dependent on the loading conditions and are not included in the propagation delay, as is the industry standard for gate drivers. output input t dlh t r 90% 10% v ih v il t f t dhl 08994-007 figure 20 . propagation delay paramet ers channel - to - channel matching refers to the maximum amount that the propagation delay differs between channels within a single adum3220 / ADUM3221 component. pr opagation delay skew refers to the maximum amount that the propagation delay differs between multiple adum3220 / ADUM3221 components operating under the same co nditions. thermal limitations and switch load characteristics for i solated gate driver s, the necessary separation between the input and output circuits prevent s the use of a single thermal pad beneath the part ; therefore , heat is dissipated mainly through the p ackage pins. package thermal dissipation limits the performance of switching frequency vs . output load , a s illustrated in figure 8 , which shows the maximum load capacitance that can be driven with a 1 ? series gate resist or for diffe rent values of output voltage. f or example , this curve shows that a typical adum3220 / ADUM3221 can drive a large mosfet with 120 nc gate charge at 8 v output (which is equivalent to a 1 5 nf load ) up to a frequency of about 300 khz. output load c haracteristics the adum3220 / ADUM3221 output signals depend on the characteristics of the output load, which is typically an n - channel mo sf e t. the driver output response to an n - channel mosfet load can be modeled with a switch output resistance (r sw ), an inductance due to the printed circuit board tr ace (l trace ) , a series gate resistor (r gate ), and a gate - to - source capacitance (c gs ) , as shown in figure 21 . adum3220/ ADUM3221 v ia v oa r sw r gate c gs l trace v o 08994-118 figure 21 . rl c m odel of the g ate of an n -c hannel mosfet r sw is the switch resi stance of the internal adum3220 / ADUM3221 driver output, which is about 1.5 ?. r gate is the intrinsic gate resistance of the mosfet and any external series resistance. a mosfet that requires a 4 a gate driver has a typical intrinsic gate resistance of about 1 ? and a gate - to - source capacitance, c gs , from 2 nf to 10 nf. l trace is the inductance of the printed circuit board trace, typically a value of 5 nh or less for a well - designed layout with a very short and wide connection from the adum3220 / ADUM3221 output to the gate of the mosfet. the following equation defines the q factor of the rlc circuit, which indicates how the adum3220 / ADUM3221 out put responds to a step change. for a well - damped output, q is less than 1. adding a series gate resist or dampens the output response. gs trace gate sw c l rr q + = ) ( 1 in figure 5 and figure 6 , the adum3220 / ADUM3221 output waveforms for 10 v output are shown for a c gs of 2 nf and 1 nf, respectively. note the ringing of the output in figure 6 with c gs of 1 nf and a calculated q factor of 1.5, where less than 1 is desir ed for good damping.
data sheet adum3220/ADUM3221 rev. c | page 13 of 16 output ringing can be reduced by adding a series gate resistor to dampen the response. for applications that use a load of 1 nf or less, it is recommended that a series gate resistor of about 5 ? be added . as shown in figure 7 , r gate is 5 ?, which yields a calculated q factor of about 0.3 . figure 7 illustrates a damped response in comparison with figure 6 . dc correctness and m agnetic field immuni ty positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. the decoder is bistable and is , therefor e , either set or reset by the pulses, indicating input logic transitions. in the absence of logic transitions of more than 1 s at the input, a periodic set of refresh pulses indicative of the correct input state is sent to ensur e dc correctness at the out put. if the decoder receives no internal pulses for more than about 3 s, the input side is assumed to be unpowered or nonfunc - tional, in which case the isolator output is forced to a default low state by the watchdog timer circuit. in addition , t he output s are in a low default state while the power is rising before the uvlo threshold is crossed. the adum3220 / ADUM3221 are immune to external magnetic fields. the l imitation on the adum3220 / ADUM3221 magnetic field immunity is set by the condition in which induced voltage in the transformer receiving coil is sufficiently la rge to either falsely set or reset the decoder. the following analysis defines the conditions under which this can occur. the 3 v operating condition of the adum3220 / ADUM3221 is examined because it represents the most susceptible mode of operation. the pulses at the transformer output have an amplitude greater than 1.0 v. the decoder has a sensing threshold at about 0.5 v, therefore establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = ( ?d / dt ) r n 2 ; n = 1, 2, ... , n where: is the magnetic flux density (gauss). r n is the radius of the nth turn in the receiving coil (cm). n is the number of turns in the receiving coil. given the geometry of the receiving coil in the adum3220 / ADUM3221 and an imposed requirement that the induced voltage be , at most , 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated, as shown in figure 22. magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0.01 1k 10k 10m 0.1 1 100m 100k 08994-009 figure 22 . maximum allowable external magnetic flux density for example, at a magnetic field frequency of 1 mhz, the maxi - mum allowable magnetic field of 0.2 kgauss i nduces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. simi - larly, if such an event were to occur during a transmitted pulse (and had the worst - case polarity), the receiv ed pulse is reduced f rom >1.0 v to 0.75 v , still well above the 0.5 v sensing thresh - old of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the adum3220 / ADUM3221 transformers. figure 23 expresses these allowable current magnitudes as a function of frequency for selected distances. as shown , the adum3220 / ADUM3221 are immune and can be a ffected only by extremely large currents operated at a high frequency very close to the co mponent. for the 1 mhz examp le, a 0.5 ka current must be placed 5 mm away from the adum3220 / ADUM3221 to affect the operation of the component . magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 08994-010 figure 23 . maximum allowable current for various current - to- adum3220 / ADUM3221 spacings
adum3220/ADUM3221 data sheet rev. c | page 14 of 16 power consumption the supply current at a given channel of the adum3220 / ADUM3221 isolator is a function of the supply voltage, channel data rate, and channel output load. for each input channel, the supply current is given by i ddi = i ddi ( q ) f 0.5 f r i ddi = i ddi ( d ) (2 f ? f r ) + i ddi (q) f > 0.5 f r f or each output channel, the supply current is given by i ddo = i ddo ( q ) f 0.5 f r i ddo = ( i ddo ( d ) + (0.5 10 ?3 ) c l v ddo ) (2 f ? f r ) + i ddo( q ) f > 0.5 f r where: i ddi (d) , i ddo (d) are the input and output dy namic supply currents per channel (ma/mbps). c l is the output load capacitance (pf). v ddo is the output supply voltage (v). f is the input logic signal frequency (mhz, half of the input data rate, nrz signaling ). f r is the input stage refresh rate (mbps ). i ddi (q) , i ddo (q) are the specified input and output quiescent supply currents (ma). to calculate the total i dd1 and i dd2 supply current, the supply currents for each input and output channel corresponding to i dd1 and i dd2 are calculated and totaled. figure 9 provides total input i dd1 supply current as a function of frequency for both input channels . figure 10 provide s total i dd2 supply cur rent as a function of frequency f or both outputs loaded with 2 nf capacitance . insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insu - lation degradation is dependent on the characteristics of t he voltage waveform applied across the insulation. in addition to the testing performed by the regulatory agencies, analog devices carries out an extensive set of evaluations to determine the lif e time of the insulation structure within the adum3220 / ADUM3221 . a nalog devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. acce l- eration factors for several ope rating conditions are determined. these factors allow calculation of the time to failure at the actual working voltage. the values shown in table 9 summarize the peak voltage for 50 years of service life . in many cases, the approved working voltage is higher than the 50- year service life voltage. operation at these high working voltages can lead to shortened insulation life in some cases. the insulation lifetime of the adum3220 / ADUM3221 depends on the voltage waveform type imposed across the isol a tion barrier. the i coupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, un ipo - lar ac, or dc. figure 24, figure 25 , and figure 26 illustrate these different isolation voltage waveforms . a b ipolar ac voltag e environment is the worst case for the i coupler products and is the 50- year operating lifetime that a nalog devices recommend s for maximum working voltage. in the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. this allows operation at higher working volt ages while still achieving a 50 - year service life. any cross - insulation voltage waveform that does not conform to figure 25 or figure 26 should be treated as a bipolar ac waveform , and its peak volt age should be limited to the 50 - year lifetime voltage value listed in table 9 . note that the voltage presented in figure 25 is shown as sinu - soidal for illustration purposes only. it is meant to represent any voltage waveform varying betw een 0 v and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0 v. 0v rated peak voltage 08994-011 figure 24 . bipolar ac waveform 0v rated peak voltage 08994-012 figure 25 . unipolar ac waveform 0v rated peak voltage 08994-013 figure 26 . dc waveform
data sheet adum3220/ADUM3221 rev. c | page 15 of 16 outline dimensions contr ollin g dimen sions are in millimeters; inch dimension s (in p arent he ses) are round ed-of f milli mete r equiv alents for r eference onl y and are not appropria te for use in des ign. compl iant t o jedec st andards ms-012-aa 012407 -a 0.25 (0.00 98) 0.17 (0.0067) 1.27 (0.05 00) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.00 99) 45 8 0 1.75 (0.0688) 1.35 (0.05 32) sea ting plane 0.25 (0.00 98) 0.10 (0.00 40) 4 1 8 5 5.00 (0.1968) 4.80 (0.18 90) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.24 41) 5.80 (0.2284) 0.51 (0.02 01) 0.31 (0.0122) copla narit y 0.10 figure 27 . 8- lead standard small outline packag e [soic_n] narrow body (r - 8) dimensions shown in millimeters and (inches) ordering guide model 1 , 2 no. of inputs, v dd1 side maximum data rate (m hz ) maximum propagation delay, 5 v (ns) minimum v dd2 operating voltage (v) output shoot - through protection (ye s/no) junction temperature range package description package option adum3220arz 2 1 60 4. 5 yes ?40c to + 125c 8 - lead soic_n r - 8 adum3220arz - rl7 2 1 60 4.5 yes ?40c to +125c 8 - lead soic_n r - 8 adum3220brz 2 1 60 7.6 yes ?40c to +125c 8 - lead soic_n r - 8 adum3220brz - rl7 2 1 60 7.6 yes ?40c to +125c 8 - lead soic_n r - 8 adum3220 w arz 2 1 60 4. 5 yes ?40c to +125c 8 - lead soic_n r - 8 adum3220 w arz - rl7 2 1 60 4.5 yes ?40c to +125c 8 - lead soic_n r - 8 adum3220 w brz 2 1 60 7.6 yes ?40c to +125c 8 - lead soic_n r - 8 adum3220 w brz - rl7 2 1 60 7.6 yes ?40c to +125c 8 - lead soic_n r - 8 ADUM3221arz 2 1 60 4. 5 no ?40c to +125c 8 - lead soic_n r - 8 ADUM3221arz - rl7 2 1 60 4.5 no ?40c to +125c 8 - lead soic_n r - 8 ADUM3221brz 2 1 60 7.6 no ?40c to +125c 8 - lead soic_n r - 8 ADUM3221brz - rl7 2 1 60 7.6 no ?40c to +125c 8 - lead soic_n r - 8 ADUM3221 w arz 2 1 60 4. 5 no ?40c to +125c 8 - lead soic_n r - 8 ADUM3221 w arz - rl7 2 1 60 4.5 no ?40c to +125c 8 - lead soic_n r - 8 ADUM3221 w brz 2 1 60 7.6 no ?40c to +125c 8 - lead soic_n r - 8 ADUM3221 w brz - rl7 2 1 60 7.6 no ?40c to +125c 8 - lead soic_n r - 8 1 z = rohs compliant part. 2 w = qualified for automotiv e applications. automotive products the adum3220w and ADUM3221w models are available with controlled manufact uring to support the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the specifications section of this data sheet carefully. only the automotive grade products shown are available for use in automotive applications. contact your local analog devices account representative for specific product ordering information and to obtain the sp ecific automotive reliability reports for these models.
adum3220/ADUM3221 data sheet rev. c | page 16 of 16 notes ? 2010 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08994 - 0 - 10/12(c)

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